In general, the epitaxial silicon wafer has excellent characteristics such that neither defects arising from oxygen nor Grown-in defects (including COP) introduced during single crystal ingot growth are included in a surface epitaxial layer thereof where the device is made.
In recent years, epitaxial silicon wafers are being used for high-performance devices such as MPUs and flash memories and high-performance power devices such as MOS FETs and IGBTs. On the other hand, high flatness is considered particularly important for improvement of semiconductor substrate quality and for preparation of a microfabrication pattern in accordance with higher integration.
As for the epitaxial growth in a wafer in which high flatness is required, improvement in layer thickness uniformity is pursued by single wafer processing. Moreover, layer thickness uniformization is further attempted by controlling the flow of gas for epitaxial growth by a partition and the like (for example, Japanese Unexamined Patent Application Publication No. 2005-353665).
However, it is likely that the edge part of a silicon single crystal wafer to serve as a substrate shows an abrupt change in the thickness of the formed epitaxial layer and hence it is difficult to secure the flatness in the edge part.
Moreover, since it is likely that the vicinity of the edge part (or the outer circumferential part) of a semiconductor wafer (for example, a silicon single crystal wafer) to serve as a substrate shows an abrupt change in the thickness of the formed epitaxial layer due to various factors, and it is difficult to achieve the layer thickness uniformity only by the uniformization of the flow of gas for epitaxial growth.
Therefore, a number of methods of optimizing epitaxial growth conditions to reduce the unevenness in the distribution of the layer thickness have been proposed, but it is hard to say that they are good enough. Since a flattening process after the epitaxial growth cannot be performed when the grown wafer is found to have unsatisfactory flatness is obtained. Therefore, such wafer is deemed to be defective so as to become a waste.
For example, a method of manufacturing an epitaxial silicon wafer is proposed in which a substrate satisfying a desired flatness is sent to a predictive process of simulating the substrate flatness after epitaxial growth, the substrate determined to satisfy the substrate flatness after the layer formation as the objective is sent to the subsequent epitaxial growth process, and the substrate determined not to satisfy the substrate flatness is sent to the flattening process again (for example, Japanese Unexamined Patent Application Publication No. 2005-353665, Japanese Unexamined Patent Application Publication No. 2001-302395).
However, Japanese Unexamined Patent Application Publication No. 2001-302395 does not disclose concretely a method of simulating film formation in the epitaxial growth. In general, simulation of the layer formation is not necessarily easy since various factors interact with each other. Therefore, it is very difficult, by using the method of Japanese Unexamined Patent Application Publication No. 2005-353665, to perform the simulation in order to predict the flatness of the epitaxial silicon wafer on which the epitaxial layer is formed.